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| AT6000/LV Series Features * * * * * * * * * * High Performance System Speeds > 100 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns/1.5 ns Input Delay 3.0 ns/6.0 ns Output Delay Up to 204 User I/Os Thousands of Registers Cache Logic(R) Design Complete/Partial In-System Reconfiguration No Loss of Data or Machine State Adaptive Hardware Low Voltage and Standard Voltage Operation 5.0 (VCC = 4.75V to 5.25V) 3.3 (VCC = 3.0V to 3.6V) Automatic Component Generators Reusable Custom Hard Macro Functions Very Low Power Consumption Standby Current of 500 A/ 200 A Typical Operating Current of 15 to 170 mA Programmable Clock Options Independently Controlled Column Clocks Independently Controlled Column Resets Clock Skew Less Than 1 ns Across Chip Independently Configurable I/O (PCI Compatible) TTL/CMOS Input Thresholds Open Collector/Tri-state Outputs Programmable Slew-Rate Control I/O Drive of 16 mA (combinable to 64 mA) Easy Migration to Atmel Gate Arrays for High Volume Production Coprocessor Field Programmable Gate Arrays Description AT6000 Series SRAM-Based Field Programmable Gate Arrays (FPGAs) are ideal for use as reconfigurable coprocessors and implementing compute intensive logic. Supporting system speeds greater than 100 MHz and using a typical operating current of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive designs. These FPGAs are designed to implement Cache Logic(R), which provides the user with the ability to implement adaptive hardware and perform hardware acceleration. The patented AT6000 Series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O. (continued) AT6000 and AT6000LV Series AT6000 Series Field Programmable Gate Arrays Device Usable Gates Cells Registers (maximum) I/O (maximum) Typ. Operating Current (mA) Cell Rows x Columns AT6002 6,000 1,024 1,024 96 15-30 32 x 32 AT6003 9,000 1,600 1,600 120 25-45 40 x 40 AT6005 15,000 3,136 3,136 108 40-80 56 x 56 AT6010 30,000 6,400 6,400 204 85-170 80 x 80 0264E 2-3 Description (Continued) Devices range in size from 4,000 to 30,000 usable gates, and 1024 to 6400 registers. Pin locations are consistent throughout the AT6000 Series for easy design migration. High-I/O versions are available for the lower gate count devices. AT6000 Series FPGAs utilize a reliable 0.6 m singlepoly, double-metal CMOS process and are 100% factorytested. Atmel's PC- and workstation-based Integrated Development System is used to create AT6000 Series designs. Multiple design entry methods are supported. The Atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, very efficient and contain the most important and most commonly used logic and wiring functions. The cell's small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing network provides fast, efficient communication over medium and long distances. Figure 1. Symmetrical Array Surrounded by I/O The Symmetrical Array At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous and completely uninterrupted from one edge to the other, except for bus repeaters spaced every eight cells (Figure 2). In addition to logic and storage, cells can also be used as wires to connect functions together over short distances and are useful for routing in tight spaces. The Busing Network There are two kinds of buses: local and express (see Figures 2 and 3). Local buses are the link between the array of cells and the busing network. There are two local buses-- North-South 1 and 2 (NS1 and NS2)-- for every column of cells, and two local buses-- East-West 1 and 2 (EW1 and EW2)-- for every row of cells. In a sector (an 8 x 8 array of cells enclosed by repeaters) each local bus is connected to every cell in its column or row, thus providing every cell in (continued) 2-4 AT6000/LV Series AT6000/LV Series Figure 2. Busing Network (one sector) CELL REPEATER Figure 3. Cell-to-Cell and Bus-to-Bus Connections 2-5 Description (Continued) the array with read/write access to two North-South and two East-West buses. Each cell, in addition, provides the ability to route a signal on a 90 turn between the NS1 bus and EW1 bus and between the NS2 bus and EW2 bus. Express buses are not connected directly to cells, and thus provide higher speeds. They are the fastest way to cover long, straight-line distances within the array. Each express bus is paired with a local bus, so there are two express buses for every column and two express buses for every row of cells. Connective units, called repeaters, spaced every eight cells, divide each bus, both local and express, into segments spanning eight cells. Repeaters are aligned in rows and columns thereby partitioning the array into 8 x 8 sectors of cells. Each repeater is associated with a local/express pair, and on each side of the repeater are connections to a local-bus segment and an express-bus segment. The repeater can be programmed to provide any one of twenty-one connecting functions. These functions are symmetric with respect to both the two repeater sides and the two types of buses. Among the functions provided are the ability to: * Isolate bus segments from one another * Connect two local-bus segments * Connect two express-bus segments * Implement a local/express transfer In all of these cases, each connection provides signal regeneration and is thus unidirectional. For bidirectional connections, the basic repeater function for the NS2 and EW2 repeaters is augmented with a special programmable connection allowing bidirectional communication between local-bus segments. This option is primarily used to implement long, tri-state buses. Figure 4. Cell Structure The Cell Structure The Atmel cell (Figure 4) is simple and small and yet can be programmed to perform all the logic and wiring functions needed to implement any digital circuit. Its four sides are functionally identical, so each cell is completely symmetrical. Read/write access to the four local buses-- NS1, EW1, NS2 and EW2-- is controlled, in part, by four bidirectional pass gates connected directly to the buses. To read a local bus, the pass gate for that bus is turned on and the three-input multiplexer is set accordingly. To write to a local bus, the pass gate for that bus and the pass gate for the associated tri-state driver are both turned on. The twoinput multiplexer supplying the control signal to the drivers permits either: (1) active drive, or (2) dynamic tri-stating controlled by the B input. Turning between LNS1 and LEW1 or between LNS2 and LEW2 is accomplished by turning on the two associated pass gates. The operations of reading, writing and turning are subject to the restriction that each bus can be involved in no more than a single operation. In addition to the four local-bus connections, a cell receives two inputs and provides two outputs to each of its North (N), South (S), East (E) and West (W) neighbors. These inputs and outputs are divided into two classes: "A" and "B." There is an A input and a B input from each neighboring cell and an A output and a B output driving all four neighbors. Between cells, an A output is always connected to an A input and a B output to a B input. Within the cell, the four A inputs and the four B inputs enter two separate, independently configurable multiplexers. Cell flexibility is enhanced by allowing each multiplexer to select also the logical constant "1." The two multiplexer outputs enter the two upstream AND gates. Downstream from these two AND gates are an ExclusiveOR (XOR) gate, a register, an AND gate, an inverter and two four-input multiplexers producing the A and B outputs. These multiplexers are controlled in tandem (unlike the A and B input multiplexers) and determine the function of the cell. * In State 0-- corresponding to the "0" inputs of the multiplexers-- the output of the left-hand upstream AND gate is connected to the cell's A output, and the output of the right-hand upstream AND gate is connected to the cell's B output. * In State 1-- corresponding to the "1" inputs of the multiplexers-- the output of the left-hand upstream AND gate is connected to the cell's B output, the output of the right-hand upstream AND gate is connected to the cell's A output. * In State 2-- corresponding to the "2" inputs of the multiplexers-- the XOR of the outputs from the two upstream AND gates is provided to the cell's A output, (continued) 2-6 AT6000/LV Series AT6000/LV Series Figure 5a. Combinatorial Physical States Li Li A Li B "0" A, L o "0" B "0" A, L o "1" B "1" A, L o "0" B "1" A, L o "1" B Figure 5c. Physical Constants A, L o A Li B B A, L o A Li B B A, L o A Li B A, L o A Li B A, L o A Li B A, L o B A, L o B A, L o B A, L o B A, L o B Figure 6a. Two-Input AND Feeding XOR A Li B A Li B Li B Li B Li B A Li A, L o B A, L o B B A, L o A, L o A, L o B A Li B A Li B A Li B A Li B A 10 A, L o A, L o B A, L o B A, L o B A, L o B Figure 5b. Register States A D Q A, L o "0" B D Q A, L o A Li B Li B D Q A, L o A Li B D Q A, L o B A Li B Figure 6b. Cell Configuration (A*L) XOR B D Q D Q A, L o A B B Li B A, L o D Q A, L o A Li B A Li B 10 D Q A, L o B D Q A, L o B D Q D Q A, L o B A, L o 2-7 Description (Continued) * while the NAND of these two outputs is provided to the cell's B output. In State 3-- corresponding to the "3" inputs of the multiplexers-- the XOR function of State 2 is provided to the D input of a D-type flip-flop, the Q output of which is connected to the cell's A output. Clock and asynchronous reset signals are supplied externally as described later. The AND of the outputs from the two upstream AND gates is provided to the cell's B output. Clock Distribution Along the top edge of the array is logic for distributing clock signals to the D flip-flop in each logic cell (Figure 7). The distribution network is organized by column and permits columns of cells to be independently clocked. At the head of each column is a user-configurable multiplexer providing the clock signal for that column. It has four inputs: * Global clock supplied through the CLOCK pin * Express bus adjacent to the distribution logic * "A" output of the cell at the head of the column * Logical constant "1" to conserve power (no clock) Through the global clock, the network provides low-skew distribution of an externally supplied clock to any or all of the columns of the array. The global clock pin is also connected directly to the array via the A input of the upper left and right corner cells (AW on the left, and AN on the right). The express bus is useful in distributing a secondary clock to multiple columns when the global clock line is used as a primary clock. The A output of a cell is useful in providing a clock signal to a single column. The constant "1" is used to reduce power dissipation in columns using no registers. Logic States The Atmel cell implements a rich and powerful set of logic functions, stemming from 44 logical cell states which permutate into 72 physical states. Some states use both A and B inputs. Other states are created by selecting the "1" input on either or both of the input multiplexers. There are 28 combinatorial primitives created from the cell's tri-state capabilities and the 20 physical states represented in the Figure 5a. Five logical primitives are derived from the physical constants shown in Figure 5c. More complex functions are created by using cells in combination. A two-input AND feeding an XOR (Figure 6a) is produced using a single cell (Figure 6b). A two-to-one multiplexer selects the logical constant "0" and feeds it to the righthand AND gate. The AND gate acts as a feed-through, letting the B input pass through to the XOR. The three-toone multiplexer on the right side selects the local-bus input, LNS1, and passes it to the left-hand AND gate. The A and LNS1 signals are the inputs to the AND gate. The output of the AND gate feeds into the XOR, producing the logic state (A*L) XOR B. Figure 7. Column Clock and Column Reset GLOBAL CLOCK "1" GLOBAL CLOCK Asynchronous Reset Along the bottom edge of the array is logic for asynchronously resetting the D flip-flops in the logic cells (Figure 7). Like the clock network, the asynchronous reset network is organized by column and permits columns to be independently reset. At the bottom of each column is a userconfigurable multiplexer providing the reset signal for that column. It has four inputs: * Global asynchronous reset supplied through the RESET pin * Express bus adjacent to the distribution logic * "A" output of the cell at the foot of the column * Logical constant "1"to conserve power The asynchronous reset logic uses these four inputs in the same way that the clock distribution logic does. Through the global asynchronous reset, any or all columns can be reset by an externally supplied signal. The global asynchronous reset pin is also connected directly to the array via the A input of the lower left and right corner cells (AS on the left, and AE on the right). The express bus can be used to distribute a secondary reset to multiple columns when the global reset line is used as a primary reset, the A output of a cell can also provide an asynchronous reset signal to a single column, and the constant "1" is used by columns with registers requiring no reset. All registers are reset during power-up. (continued) A D Q CELL EXPRESS BUS D Q CELL D E D I C A T E D EXPRESS BUS B U R I E D R O U T I N G CELL D Q EXPRESS BUS CELL D Q A "1" GLOBAL RESET GLOBAL RESET EXPRESS BUS 2-8 AT6000/LV Series AT6000/LV Series Description (Continued) Input/Output The Atmel architecture provides a flexible interface between the logic array, the configuration control logic and the I/O pins. Two adjacent cells-- an "exit" and an "entrance" cell-- on the perimeter of the logic array are associated with each I/O pin. There are two types of I/Os: A-type (Figure 8a) and B-type (Figure 8b). For A-type I/Os, the edge-facing A output of an exit cell is connected to an output driver, and the edgefacing A input of the adjacent entrance cell is connected to an input buffer. The output of the output driver and the input of the input buffer are connected to a common pin. B-type I/Os are the same as A-type I/Os, but use the B inputs and outputs of their respective entrance and exit cells. A- and B-type I/Os alternate around the array. Control of the I/O logic is provided by user-configurable memory bits. TTL/CMOS Inputs puts that are not speed-critical. Fast and slow slew rates have the same DC-current sinking capabilities, but the rate at which each allows the output devices to reach full drive differs. Pull-up A user-configurable bit controls the pull-up transistor in the I/O pin. It's primary function is to provide a logical "1" to unused input pins. When on, it is approximately equivalent to a 25K resistor to VCC. Enable Select User-configurable bits determine the output-enable for the output driver. The output driver can be static - - always on or always off - - or dynamically controlled by a signal generated in the array. Four options are available from the array: (1) the control is low and always driving; (2) the control is high and never driving; (3) the control is connected to a vertical local bus associated with the output cell; or (4) the control is connected to a horizontal local bus associated with the output cell. On power-up, the user I/Os are configured as inputs with pull-up resistors. In addition to the functionality provided by the I/O logic, the entrance and exit cells provide the ability to register both inputs and outputs. Also, these perimeter cells (unlike interior cells) are connected directly to express buses: the edge-facing A and B outputs of the entrance cell are connected to express buses, as are the edge-facing A and B inputs of the exit cell. These buses are perpendicular to the edge, and provide a rapid means of bringing I/O signals to and from the array interior and the opposite edge of the chip. A user-configurable bit determines the threshold level-- TTL or CMOS-- of the input buffer. Open Collector/Tri-state Outputs A user-configurable bit which enables or disables the active pull-up of the output device. Slew Rate Control A user-configurable bit controls the slew rate-- fast or slow-- of the output buffer. A slow slew rate, which reduces noise and ground bounce, is recommended for out- Figure 8a. A-Type I/O Logic Figure 8b. B-Type I/O Logic 2-9 Chip Configuration The Integrated Development System generates the SRAM bit pattern required to configure a AT6000 Series device. A PC parallel port, microprocessor, EPROM or serial configuration memory can be used to download configuration patterns. Users select from several configuration modes. Many factors, including board area, configuration speed and the number of designs implemented in parallel can influence the user's final choice. Configuration is controlled by dedicated configuration pins and dual-function pins that double as I/O pins when the device is in operation. The number of dual-function pins required for each mode varies. The devices can be partially reconfigured while in operation. Portions of the device not being modified remain operational during reconfiguration. Simultaneous configuration of more than one device is also possible. Full configuration takes as little as a millisecond, partial configuration is even faster. Refer to the Pin Function Description section following for a brief summary of the pins used in configuration. For more information about configuration, refer to the AT6000 Series Configuration data sheet. CON is then released. CON is an open collector signal. After power-up initialization, forcing CON low begins the configuration process. CS Configuration enable pin. All configuration pins are ignored if CS is high. CS must be held low throughout the configuration process. CS is a TTL input pin. M0, M1, M2 Configuration mode pins are used to determine the configuration mode. All three are TTL input pins. CCLK Configuration clock pin. CCLK is a TTL input or a CMOS output depending on the mode of operation. In modes 1, 2, 3, and 6 it is an input. In modes 4 and 5 it is an output with a typical frequency of 1 MHz. In all modes, the rising edge of the CCLK signal is used to sample inputs and change outputs. CLOCK External logic source used to drive the internal global clock line. Registers toggle on the rising edge of CLOCK. The CLOCK signal is neither used nor affected by the configuration modes. It is always a TTL input. RESET Pin Function Description This section provides abbreviated descriptions of the various AT6000 Series pins. For more complete descriptions, refer to the AT6000 Series Configuration data sheet. Pinout tables for the AT6000 series of devices follow. Array register asynchronous reset. RESET drives the internal global reset. The RESET signal is neither used nor affected by the configuration modes. It is always a TTL input. Dual-Function Pins When CON is high, dual-function I/O pins act as device I/Os; when CON is low, dual-function pins are used as configuration control or data signals as determined by the configuration modes. Care must be taken when using these pins to ensure that configuration activity does not interfere with other circuitry connected to these pins in the application. D0 or I/O Power Pins VCC, VDD, GND, VSS VCC and GND are the I/O supply pins, VDD and VSS are the internal logic supply pins. VCC and VDD should be tied to the same trace on the printed circuit board. GND and VSS should be tied to the same trace on the printed circuit board. Input/Output Pins All I/O pins can be used in the same way (refer to the I/O section of the architecture description). Some I/O pins are dual-function pins used during configuration of the array. When not being used for configuration, dual-function I/Os are fully functional as normal I/O pins. On initial power-up, all I/Os are configured as TTL inputs with a pull-up. Serial configuration modes use D0 as the serial data input pin. Parallel configuration modes use D0 as the least-significant bit. Input data must meet setup and hold requirements with respect to the rising edge of CCLK. D0 is a TTL input during configuration. D1 to D7 or I/O Dedicated Timing and Control Pins CON Parallel configuration modes use these pins as inputs. Serial configuration modes do not use them. Data must meet setup and hold requirements with respect to the rising edge of CCLK. D1-D7 are TTL inputs during configuration. Configuration-in-process pin. After power-up, CON staysLow until power-up initialization is complete, at which time (continued) 2-10 AT6000/LV Series AT6000/LV Series Pin Function Description (Continued) A0 to A16 or I/O During configuration in modes 1, 2 and 5, these pins are CMOS outputs and act as the address pins for a parallel EPROM. A0-A16 eliminates the need for an external address counter when using an external parallel nonvolatile memory to configure the FPGA. Addresses change after the rising edge of the CCLK signal. CSOUT or I/O to D0 (or D0-D7, in parallel mode) is compared with the current contents of the internal configuration RAM. If a mismatch is detected between the data being loaded and the data already in the RAM, the ERR pin goes low. The CHECK function is optional and can be disabled during initial programming. ERR or I/O When cascading devices, CSOUT is an output used to enable other devices. CSOUT should be connected to the CS input of the downstream device. The CSOUT function is optional and can be disabled during initial programming when cascading is not used. When cascading devices, CSOUT should be dedicated to configuration and not used as a configurable I/O. CHECK or I/O During configuration, ERR is an output. When the CHECK function is activated and a mismatch is detected between the current configuration data stream and the data already loaded in the configuration RAM, ERR goes low. The ERR output is a registered signal. Once a mismatch is found, the signal is set and is only reset after the configuration cycle is restarted. ERR is also asserted for configuration file errors. The ERR function is optional and can be disabled during initial programming. During configuration, CHECK is a TTL input that can be used to enable the data check function at the beginning of a configuration cycle. No data is written to the device while CHECK is low. Instead, the configuration file being applied Device Pinout Selection (Max. Number of User I/O) AT6002 84 PLCC 100 VQFP 132 PQFP 144 TQFP 208 PQFP 240 PQFP 64 I/O 80 I/O 96 I/O 96 I/O -- -- AT6003 64 I/O 80 I/O 108 I/O 120 I/O -- -- AT6005 64 I/O 80 I/O 108 I/O 108 I/O -- -- AT6010 -- -- 108 I/O 120 I/O 172 I/O 204 I/O Bit-Stream Sizes Mode(s) 1 2 3 4 5 6 Type (1, 2) P P S S P P Beginning Sequence Preamble Preamble Null Byte/Preamble Null Byte/Preamble Preamble Preamble/Preamble AT6002 2677 2677 2678 2678 2677 2678 AT6003 4153 4153 4154 4154 4153 4154 AT6005 8077 8077 8078 8078 8077 8078 AT6010 16393 16393 16394 16394 16393 16394 Notes: 1. P = Parallel. 2. S = Serial. 2-11 Pinout Assignment Left Side (Top to Bottom) AT6002 -- I/O24(A) or A7 -- -- -- -- -- -- I/O23(A) or A6 -- -- I/O22(B) I/O21(A) or A5 -- -- I/O20(B) I/O19(A) or A4 -- I/O18(B) I/O17(A) or A3 I/O16(B) -- I/O15(A) or A2 -- GND VSS I/O14(A) or A1 -- -- I/O13(A) or A0 I/O12(B) or D7 -- I/O11(A) or D6 I/O10(A) or D5 VDD VCC I/O9(B) -- I/O8(A) or D4 I/O7(B) -- -- I/O6(A) or D3 -- -- GND -- -- I/O5(A) or D2 I/O4(B) -- I/O30(A) or A7 I/O29(B) -- -- -- -- I/O28(A) I/O27(A) or A6 -- -- I/O26(A) I/O25(A) or A5 -- -- I/O24(B) I/O23(A) or A4 -- I/O22(B) I/O21(A) or A3 I/O20(B) -- I/O19(A) or A2 I/O18(B) GND VSS I/O17(A) or A1 -- I/O16(B) I/O15(A) or A0 I/O14(A) or D7 -- I/O13(A) or D6 I/O12(A) or D5 VDD VCC I/O11(B) -- I/O10(A) or D4 I/O9(B) -- -- I/O8(A) or D3 I/07(B) -- GND -- -- I/O6(A) or D2 I/O5(B) AT6003 -- AT6005 I/O27(A) or A7 -- -- -- -- -- I/O26(A) I/O25(A) or A6 -- -- I/O24(A) I/O23(A) or A5 -- -- I/O22(A) I/O21(A) or A4 -- I/O20(A) I/O19(A) or A3 I/O18(A) -- I/O17(A) or A2 I/O16(A) GND VSS I/O15(A) or A1 -- -- I/O14(A) or A0 I/O13(A) or D7 -- I/O12(A) or D6 I/O11(A) or D5 VDD VCC I/O10(A) -- I/O9(A) or D4 I/O8(A) -- -- I/O7(A) or D3 I/O6(A) -- GND -- -- I/O5(A) or D2 I/O4(A) AT6010 I/O51(A) I/O50(A) or A7 I/O49(A) I/O48(B) VCC I/O47(A) GND I/O46(A) I/O45(A) or A6 I/O44(B) I/O43(A) I/O42(A) I/O41(A) or A5 I/O40(B) I/O39(A) I/O38(A) I/O37(A) or A4 I/O36(B) I/O35(A) I/O34(A) or A3 I/O33(A) I/O32(B) I/O31(A) or A2 I/O30(A) GND VSS I/O29(A) or A1 I/O28(B) I/O27(A) I/O26(A) or A0 I/O25(A) or D7 I/O24(B) I/O23(A) or D6 I/O22(A) or D5 VDD VCC I/O21(A) I/O20(B) I/O19(A) or D4 I/O18(A) I/O17(A) I/O16(B) I/O15(A) or D3 I/014(A) I/O13(A) GND VSS I/O12(B) I/O11(A) or D2 I/O10(A) 84 100 132 144 PLCC VQFP PQFP TQFP -- 12 -- -- -- -- -- -- 13 -- -- -- 14 -- -- -- 15 -- -- 16 -- -- 17 -- 18 19 20 -- -- 21 22 -- 23 24 25 26 -- -- 27 -- -- -- 28 -- -- -- -- -- 29 -- -- 1 -- -- -- -- -- -- 2 -- -- -- 3 -- -- 4 5 -- -- 6 7 -- 8 -- 9 10 11 -- -- 12 13 -- 14 15 16 17 -- -- 18 19 -- -- 20 -- -- -- -- -- 21 22 -- 18 -- -- -- -- -- 19 20 -- -- 21 22 -- -- 23 24 -- 25 26 27 -- 28 29 30 31 32 -- -- 33 34 -- 35 36 37 38 39 -- 40 41 -- -- 42 43 -- 44 -- -- 45 46 -- 1 2 -- -- -- -- 3 4 -- -- 5 6 -- -- 7 8 -- 9 10 11 -- 12 13 14 15 16 -- 17 18 19 -- 20 21 22 23 24 -- 25 26 -- -- 27 28 -- 29 -- -- 30 31 180 CPGA B1 C1 D1 -- PWR (1) E1 GND (2) G1 H1 -- C2 D2 E2 -- F2 G2 H2 -- D3 E3 F3 -- G3 H3 GND (2) GND (2) F4 -- G4 H4 H5 -- J4 K4 PWR (1) PWR (1) J3 -- K3 L3 M3 -- N3 J2 K2 GND (2) GND (2) -- M2 N2 208 240 PQFP PQFP 1 2 3 -- 4 5 6 7 8 -- 9 10 11 -- 12 13 14 -- 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 -- 38 39 40 41 42 -- 43 44 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (continued) 2-12 AT6000/LV Series AT6000/LV Series Pinout Assignment (Continued) Left Side (Top to Bottom) (Continued) AT6002 -- -- I/O3(A) or D1 I/O2(B) -- -- -- I/O1(A) or D0 -- CCLK -- -- I/O4(A) or D1 I/O3(A) -- -- I/O2(B) I/O1(A) or D0 -- CCLK AT6003 -- -- AT6005 AT6010 I/O9(A) I/O8(B) I/O7(A) or D1 I/O6(A) I/O5(A) I/O4(B) I/O3(A) I/O2(A) or D0 I/O1(A) CCLK 84 100 132 144 PLCC VQFP PQFP TQFP -- -- 30 -- -- -- -- 31 -- 32 -- -- 23 -- -- -- -- 24 -- 25 -- -- 47 48 -- -- -- 49 -- 50 -- -- 32 33 -- -- 34 35 -- 36 180 CPGA P2 -- J1 K1 L1 -- M1 N1 P1 R1 208 240 PQFP PQFP 45 -- 46 47 48 -- 49 50 51 52 51 52 53 54 55 56 57 58 59 60 I/O3(A) or D1 I/O2(A) -- -- -- I/O1(A) or D0 -- CCLK Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12. 2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6. Bottom Side (Left to Right) AT6002 CON -- I/O96(A) -- -- -- -- -- -- I/O95(A) or CSOUT -- -- I/O94(B) I/O93(A) -- -- I/O92(B) I/O91(A) or CHECK -- I/O90(B) I/O89(A) or ERR I/O88(B) -- I/O87(A) GND I/O86(A) -- -- I/O85(A) CS I/O84(B) -- I/O120(A) I/O119(B) -- -- -- -- I/O118(A) I/O117(A) or CSOUT -- -- I/O116(A) I/O115(A) -- -- I/O114(B) I/O113(A) or CHECK -- I/O112(B) I/O111(A) or ERR I/O110(B) -- I/O109(A) I/O108(B) GND I/O107(A) -- I/O106(B) I/O105(A) CS I/O104(A) AT6003 CON -- AT6005 CON I/O108(A) -- -- -- -- -- I/O107(A) I/O106(A) or CSOUT -- -- I/O105(A) I/O104(A) -- -- I/O103(A) I/O102(A) or CHECK -- I/O101(A) I/O100(A) or ERR I/O99(A) -- I/O98(A) I/O97(A) GND I/O96(A) -- -- I/O95(A) CS I/O94(A) AT6010 CON I/O204(A) I/O203(A) I/O202(A) I/O201(B) VCC I/O200(A) GND I/O199(A) I/O198(A) or CSOUT I/O197(B) I/O196(A) I/O195(A) I/O194(A) I/O193(B) I/O192(A) I/O191(A) I/O190(A) or CHECK I/O189(B) I/O188(A) I/O187(A) or ERR I/O186(A) I/O185(B) I/O184(A) I/O183(A) GND I/O182(A) I/O181(B) I/O180(A) I/O179(A) CS I/O178(A) 84 100 132 144 PLCC VQFP PQFP TQFP 33 -- 34 -- -- -- -- -- -- 35 -- -- -- 36 -- -- -- 37 -- -- 38 -- -- 39 40 41 -- -- 42 43 44 26 -- 27 -- -- -- -- -- -- 28 -- -- -- 29 -- -- 30 31 -- -- 32 33 -- 34 35 36 -- -- 37 38 39 51 -- 52 -- -- -- -- -- 53 54 -- -- 55 56 -- -- 57 58 -- 59 60 61 -- 62 63 64 65 -- -- 66 67 68 37 -- 38 39 -- -- -- -- 40 41 -- -- 42 43 -- -- 44 45 -- 46 47 48 -- 49 50 51 52 -- 53 54 55 56 180 CPGA M5 M6 M7 R2 -- PWR (1) R3 GND (2) R5 R6 -- R7 P3 P4 -- P5 P6 P7 -- N4 N5 N6 -- N7 M8 GND (2) M9 -- M10 M11 L8 M12 208 240 PQFP PQFP 53 54 55 56 -- 57 58 59 60 61 -- 62 63 64 -- 65 66 67 -- 68 69 70 71 72 73 74 75 76 77 78 79 80 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 (continued) 2-13 Pinout Assignment (Continued) Bottom Side (Left to Right) (Continued) AT6002 -- I/O83(A) -- VCC I/O82(A) I/O81(B) -- I/O80(A) I/O79(B) -- -- I/O78(A) -- -- GND -- I/O77(A) I/O76(B) -- -- I/O75(A) I/O74(B) -- -- -- I/O73(A) -- RESET -- I/O103(A) -- VCC I/O102(A) I/O101(B) -- I/O100(A) I/O99(B) -- -- I/O98(A) I/O97(B) -- GND -- I/O96(A) I/O95(B) -- -- I/O94(A) I/O93(A) -- -- I/O92(B) I/O91(A) -- RESET AT6003 -- AT6005 I/O93(A) -- VCC I/O92(A) I/O91(A) -- I/O90(A) I/O89(A) -- -- I/O88(A) I/O87(A) -- GND -- I/O86(A) I/O85(A) -- -- I/O84(A) I/O83(A) -- -- -- I/O82(A) -- RESET AT6010 I/O177(B) I/O176(A) VDD VCC I/O175(A) I/O174(A) I/O173(B) I/O172(A) I/O171(A) I/O170(A) I/O169(B) I/O168(A) I/O167(A) I/O166(A) GND I/O165(B) I/O164(A) I/O163(A) I/O162(A) I/O161(B) I/O160(A) I/O159(A) I/O158(A) I/O157(B) I/O156(A) I/O155(A) I/O154(A) RESET 84 100 132 144 PLCC VQFP PQFP TQFP -- 45 -- 46 47 -- -- 48 -- -- -- 49 -- -- -- -- 50 -- -- -- 51 -- -- -- -- 52 -- 53 -- 40 -- 41 42 -- -- 43 44 -- -- 45 -- -- -- -- 46 47 -- -- 48 -- -- -- -- 49 -- 50 -- 69 -- 70 71 72 -- 73 74 -- -- 75 76 -- 77 -- 78 79 -- -- 80 81 -- -- -- 82 -- 83 -- 57 -- 58 59 60 -- 61 62 -- -- 63 64 -- 65 -- 66 67 -- -- 68 69 -- -- 70 71 -- 72 180 CPGA -- N8 PWR (1) PWR (1) N11 N12 -- N13 P8 P9 -- P10 P11 P12 GND (2) -- P13 P14 R8 -- R9 R10 R11 -- R12 R13 R14 R15 208 240 PQFP PQFP 81 82 83 84 85 86 87 88 89 90 -- 91 92 93 94 -- 95 96 97 -- 98 99 100 -- 101 102 103 104 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12. 2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6. Right Side (Bottom to Top) 84 100 132 144 PLCC VQFP PQFP TQFP -- 54 -- -- -- -- -- -- 55 -- -- -- 56 -- -- 51 -- -- -- -- -- -- 52 -- -- -- 53 -- -- 84 85 (3) -- -- -- -- 85 (4) 86 -- -- 87 88 -- -- 73 74 -- -- -- -- 75 76 -- -- 77 78 -- AT6002 -- I/O72(A) -- -- -- -- -- -- I/O71(A) -- -- I/O70(B) I/O69(A) -- -- AT6003 -- I/O90(A) I/O89(B) -- -- -- -- I/O88(A) I/O87(A) -- -- I/O86(A) I/O85(A) -- AT6005 I/O81(A) I/O80(A) -- -- -- -- -- I/O79(A) -- -- I/O78(A) I/O77(A) -- AT6010 I/O153(A) I/O152(A) I/O151(A) I/O150(B) VCC I/O149(A) GND I/O148(A) I/O147(A) I/O146(B) I/O145(A) I/O144(A) I/O143(A) I/O142(B) 180 CPGA P15 N15 M15 -- PWR (1) L15 GND (2) J15 H15 -- N14 M14 L14 -- 208 240 PQFP PQFP 105 106 107 -- 108 109 110 111 112 -- 113 114 115 -- 121 122 123 124 125 126 127 128 129 130 131 132 133 134 (continued) 2-14 AT6000/LV Series AT6000/LV Series Pinout Assignment (Continued) Right Side (Bottom to Top) (Continued) AT6002 -- I/O68(B) I/O67(A) -- I/O66(B) I/O65(A) I/O64(B) -- I/O63(A) -- GND VSS I/O62(A) -- -- I/O61(A) I/O60(B) -- I/O59(A) I/O58(A) VDD VCC I/O57(B) -- I/O56(A) I/O55(B) -- -- I/O54(A) -- -- GND -- -- I/O53(A) I/O52(B) -- -- I/O51(A) I/O50(B) -- -- -- I/O49(A) -- M2 -- I/O84(B) I/O83(A) -- I/O82(B) I/O81(A) I/O80(B) -- I/O79(A) I/O78(B) GND VSS I/O77(A) -- I/O76(B) I/O75(A) I/O74(A) -- I/O73(A) I/O72(A) VDD VCC I/O71(B) -- I/O70(A) I/O69(B) -- -- I/O68(A) I/O67(B) -- GND -- -- I/O66(A) I/O65(B) -- -- I/O64(A) I/O63(A) -- -- I/O62(B) I/O61(A) -- M2 AT6003 -- AT6005 I/O76(A) I/O75(A) -- I/O74(A) I/O73(A) I/O72(A) -- I/O71(A) I/O70(A) GND VSS I/O69(A) -- -- I/O68(A) I/O67(A) -- I/O66(A) I/O65(A) VDD VCC I/O64(A) -- I/O63(A) I/O62(A) -- -- I/O61(A) I/O60(A) -- GND -- -- I/O59(A) I/O58(A) -- -- I/O57(A) I/O56(A) -- -- -- I/O55(A) -- M2 AT6010 I/O141(A) I/O140(A) I/O139(A) I/O138(B) I/O137(A) I/O136(A) I/O135(A) I/O134(B) I/O133(A) I/O132(A) GND VSS I/O131(A) I/O130(B) I/O129(A) I/O128(A) I/O127(A) I/O126(B) I/O125(A) I/O124(A) VDD VCC I/O123(A) I/O122(B) I/O121(A) I/O120(A) I/O119(A) I/O118(B) I/O117(A) I/O116(A) I/O115(A) GND VSS I/O114(B) I/O113(A) I/O112(A) I/O111(A) I/O110(B) I/O109(A) I/O108(A) I/O107(A) I/O106(B) I/O105(A) I/O104(A) I/O103(A) M2 84 100 132 144 PLCC VQFP PQFP TQFP -- -- 57 -- -- 58 -- -- 59 -- 60 61 62 -- -- 63 64 -- 65 66 67 68 -- -- 69 -- -- -- 70 -- -- -- -- -- 71 -- -- -- 72 -- -- -- -- 73 -- 74 -- 54 55 -- -- 56 57 -- 58 -- 59 60 61 -- -- 62 63 -- 64 65 66 67 -- -- 68 69 -- -- 70 -- -- -- -- -- 71 72 -- -- 73 -- -- -- -- 74 -- 75 108 109 -- 110 -- -- 111 112 -- -- 113 114 -- -- -- 115 -- 116 -- 89 90 -- 91 92 93 -- 94 95 96 97 98 -- -- 99 100 -- 101 102 103 104 105 -- 106 107 -- -- 79 80 -- 81 82 83 -- 84 85 86 87 88 -- 89 90 91 -- 92 93 94 95 96 -- 97 98 -- -- 99 100 -- 101 -- -- 102 103 -- -- 104 105 -- -- 106 107 -- 108 180 CPGA K14 J14 H14 -- M13 L13 K13 -- J13 H13 GND (2) GND (2) K12 -- J12 H12 H11 -- G12 F12 PWR(1) PWR(1) G13 -- F13 E13 D13 -- C13 G14 F14 GND (2) GND (2) -- D14 C14 B14 -- G15 F15 E15 -- D15 C15 B15 A15 208 240 PQFP PQFP 116 117 118 -- 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 -- 142 143 144 145 146 -- 147 148 149 -- 150 151 152 -- 153 154 155 156 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12. 2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6. 3. 85 = Pin 85 on AT6005. 4. 85 = pin 85 on AT6003 and AT6010. 2-15 Pinout Assignment (Continued) Top Side (Right to Left) AT6002 M1 -- I/O48(A) -- -- -- -- -- -- I/O47(A) -- -- I/O46(B) I/O45(A) -- -- I/O44(B) I/O43(A) -- I/O42(B) I/O41(A) I/O40(B) -- I/O39(A) -- GND I/O38(A) -- -- I/O37(A) or A16 CLOCK I/O36(B) or A15 -- I/O35(A) or A14 -- VCC I/O34(A) or A13 I/O33(B) -- I/O32(A) or A12 I/O31(B) -- -- I/O30(A) or A11 -- -- GND -- I/O29(A) or A10 M1 -- I/O60(A) I/O59(B) -- -- -- -- I/O58(A) I/O57(A) -- -- I/O56(A) I/O55(A) -- -- I/O54(B) I/O53(A) -- I/O52(B) I/O51(A) I/O50(B) -- I/O49(A) I/O48(B) GND I/O47(A) -- I/O46(B) I/O45(A) or A16 CLOCK I/O44(A) or A15 -- I/O43(A) or A14 -- VCC I/O42(A) or A13 I/O41(B) -- I/O40(A) or A12 I/O39(B) -- -- I/O38(A) or A11 I/O37(B) -- GND -- I/O36(A) or A10 AT6003 M1 -- AT6005 M1 AT6010 I/O102(A) I/O101(A) I/O100(A) I/O99(B) VCC I/O98(A) GND I/O97(A) I/O96(A) I/O95(B) I/O94(A) I/O93(A) I/O92(A) I/O91(B) I/O90(A) I/O89(A) I/O88(A) I/O87(B) I/O86(A) I/O85(A) I/O84(A) I/O83(B) I/O82(A) I/O81(A) GND I/O80(A) I/O79(B) I/O78(A) I/O77(A) or A16 CLOCK I/O76(A) or A15 I/O75(B) I/O74(A) or A14 VDD VCC I/O73(A) or A13 I/O72(A) I/O71(B) I/O70(A) or A12 I/O69(A) I/O68(A) I/O67(B) I/O66(A) or A11 I/O65(A) I/O64(A) GND I/O63(B) I/O62(A) or A10 84 100 132 144 PLCC VQFP PQFP TQFP 75 -- 76 -- -- -- -- -- -- 77 -- -- -- 78 -- -- -- 79 -- -- 80 -- -- 81 -- 82 83 -- -- 84 1 2 -- 3 -- 4 5 -- -- 6 -- -- -- 7 -- -- -- -- 8 76 -- 77 -- -- -- -- -- -- 78 -- -- -- 79 -- -- 80 81 -- -- 82 83 -- 84 -- 85 86 -- -- 87 88 89 -- 90 -- 91 92 -- -- 93 94 -- -- 95 -- -- -- -- 96 117 -- 118 -- -- -- -- -- 119 120 -- -- 121 122 -- -- 123 124 -- 125 126 127 -- 128 129 130 131 -- -- 132 1 2 -- 3 -- 4 5 6 -- 7 8 -- -- 9 10 -- 11 -- 12 109 -- 110 111 -- -- -- -- 112 113 -- -- 114 115 -- -- 116 117 -- 118 119 120 -- 121 122 123 124 -- 125 126 127 128 -- 129 -- 130 131 132 -- 133 134 -- -- 135 136 -- 137 -- 138 180 CPGA D11 D10 D9 A14 -- PWR (1) A13 GND (2) A11 A10 -- A9 B13 B12 -- B11 B10 B9 -- C12 C11 C10 -- C9 D8 GND (2) D7 -- D6 D5 E8 D4 -- C8 PWR (1) PWR (1) C5 C4 -- C3 B8 B7 -- B6 B5 B4 GND (2) -- B3 208 240 PQFP PQFP 157 158 159 160 -- 161 162 163 164 165 -- 166 167 168 -- 169 170 171 -- 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 -- 195 196 197 198 -- 199 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 I/O54(A) -- -- -- -- -- I/O53(A) I/O52(A) -- -- I/O51(A) I/O50(A) -- -- I/O49(A) I/O48(A) -- I/O47(A) I/O46(A) I/O45(A) -- I/O44(A) I/O43(A) GND I/O42(A) -- -- I/O41(A) or A16 CLOCK I/O40(A) or A15 -- I/O39(A) or A14 -- VCC I/O38(A) or A13 I/O37(A) -- I/O36(A) or A12 I/O35(A) -- -- I/O34(A) or A11 I/O33(A) -- GND -- I/O32(A) or A10 (continued) 2-16 AT6000/LV Series AT6000/LV Series Pinout Assignment (Continued) Top Side (Right to Left) (Continued) AT6002 I/O28(B) -- -- I/O27(A) or A9 I/O26(B) -- -- -- I/O25(A) or A8 -- -- I/O34(A) or A9 I/O33(A) -- -- I/O32(B) I/O31(A) or A8 -- M0 AT6003 I/O35(B) -- -- AT6005 I/O31(A) AT6010 I/O61(A) I/O60(A) I/O59(B) I/O58(A) or A9 I/O57(A) I/O56(A) I/O55(B) I/O54(A) I/O53(A) or A8 I/O52(A) M0 84 100 132 144 PLCC VQFP PQFP TQFP -- -- -- 9 -- -- -- -- 10 -- 11 97 -- -- 98 -- -- -- -- 99 -- 100 13 -- -- 14 15 -- -- -- 16 -- 17 139 -- -- 140 141 -- -- 142 143 -- 144 180 CPGA B2 A8 -- A7 A6 A5 -- A4 A3 A2 A1 208 240 PQFP PQFP 200 201 -- 202 203 204 -- 205 206 207 208 230 231 232 233 234 235 236 237 238 239 240 I/O30(A) or A9 I/O29(A) -- -- -- I/O28(A) or A8 -- M0 -- M0 Notes: 1. PWR = Pins connected to power plane = F1, E4/E5, L2, R4, K15, L12, E14, A12. 2. GND = Pins connected to ground plane = L4, M4, N9, N10, E12, D12, C7, C6. 2-17 AC Timing Characteristics - 5V Operation Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds. Worst case: Vcc = 4.75V to 5.25V. Temperature = 0C to 70C. Cell Function Wire (4) NAND XOR AND MUX D-Flip-Flop (5) D-Flip-Flop D-Flip-Flop Bus Driver Repeater Column Clock Column Reset Clock Buffer Reset Buffer TTL Input CMOS Fast (1) (5) (5) (5) Parameter tPD (max) (4) tPD (max) tPD (max) tPD (max) tPD (max) tsetup (min) thold (min) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPXZ (max) tPZX (max) tPZX (max) Cell Types From A, B, L A, B, L A, B, L A, B, L A, B L A, B, L CLK CLK A L, E L, E GCLK, A, ES GRES, A, EN CLOCK PIN RESET PIN I/O I/O A A L L L To A, B B A B A A CLK A, B, L A L E L CLK RES GCLK GRES A A I/O PIN I/O PIN I/O PIN I/O PIN I/O PIN Load Definition 1 1 1 1 1 1 -1 0.8 1.6 1.8 1.7 1.7 2.1 1.5 0.0 -2 1.2 2.2 2.4 2.2 2.3 3.0 2.0 0.0 2.0 2.6 1.6 2.1 2.4 2.4 2.0 1.9 1.2 1.4 3.5 8.0 3.3 4.0 8.5 -4 1.8 3.2 4.0 3.2 4.0 4.9 3.0 0.0 3.0 4.0 2.3 3.0 3.0 3.0 2.9 2.8 1.5 2.3 6.0 12.0 5.5 6.5 12.5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 2 3 2 3 3 1.5 2.0 1.3 1.7 1.8 1.8 1.6 1.5 3 3 4 4 4 4 4 Outputs A, B L CLK 1.0 1.3 3.3 7.5 3.1 3.8 8.2 Input (2) (3) Output (3) Disable (5) (3, 5) Slow Output Output Slow Fast Enable Enable (3, 5) Device Cell (6) Bus (6) Column Clock (6) Icc (max) 4.5 A/MHz 2.5 A/MHz 40 A/MHz Load Definition: 1. Load of one A or B input 2. Load of one L input 3. Constant Load 4. Tester Load of 50 pF Wire, XWire, Half-Adder, Flip-Flop Wire, XWire, Half-Adder, Flip-Flop, Repeater Column Clock Driver Notes: 1. TTL buffer delays are measured from a VIH of 1.5V at the pad to the internal V IH at A. The input buffer load is constant. 2. CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant. 3. Buffer delay is to a pad voltage of 1.5V with one output switching. 4. Max specifications are the average of max tPDLH and tPDHL. 5. Parameter based on characterization and simulation; not tested in production. 6. Exact power calculation is available in an Atmel application note. = Preliminary Information 2-18 AT6000/LV Series AT6000/LV Series AC Timing Characteristics - 3.3V Operation Delays are based on fixed load. Loads for each type of device are described in the notes. Delays are in nanoseconds. Worst case: Vcc = 3.0V to 3.6V. Temperature = 0C to 70C. Cell Function Wire XOR AND MUX D-Flip-Flop (5) D-Flip-Flop D-Flip-Flop Bus Driver Repeater Column Clock Column Reset Clock Buffer Reset Buffer TTL Input CMOS Fast (1) (5) (5) (5) (4) Parameter tPD (max) (4) tPD (max) tPD (max) tPD (max) tPD (max) tsetup (min) thold (min) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPXZ (max) tPZX (max) tPZX (max) From A, B, L A, B, L A, B, L A, B, L A, B L A, B, L CLK CLK A L, E L, E GCLK, A, ES GRES, A, EN CLOCK PIN RESET PIN I/O I/O A A L L L To A, B B A B A A CLK A, B, L A L E L CLK RES GCLK GRES A A I/O PIN I/O PIN I/O PIN I/O PIN I/O PIN Load Definition 1 1 1 1 1 1 -4 1.8 3.2 4.0 3.2 4.0 4.9 3.0 0.0 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NAND 1 2 3 2 3 3 4 5 3 3 6 6 6 6 6 3.0 4.0 2.3 3.0 3.0 3.0 2.9 2.8 1.5 2.3 6.0 12.0 5.5 6.5 12.5 Input (2) (3) Output (3) Disable (5) (3, 5) Slow Output Output Slow Fast Enable Enable (3, 5) Device Cell (6) Bus (6) Column Clock (6) Cell Types Wire, XWire, Half-Adder, Flip-Flop Wire, XWire, Half-Adder, Flip-Flop, Repeater Column Clock Driver Outputs A, B L CLK Icc (max) 2.3 A/MHz 1.3 A/MHz 20 A/MHz Notes: 1. TTL buffer delays are measured from a VIH of 1.5V at the pad to the internal VIH at A. The input buffer load is constant. 2. CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant. 3. Buffer delay is to a pad voltage of 1.5V with one output switching. 4. Max specifications are the average of max tPDLH and tPDHL. 5. Parameter based on characterization and simulation; not tested in production. 6. Exact power calculation is available in an Atmel application note. Load Definition: 1. Load of one A or B input 2. Load of one L input 3. Constant Load 4. Load of 28 Clock Columns 5. Load of 28 Reset Columns 6. Tester Load of 50 pF 2-19 Absolute Maximum Ratings* Supply Voltage (VCC)......................... -0.5V to +7.0V DC Input Voltage (VIN)...............-0.5V to VCC + 0.5V DC Output Voltage (VON)...........-0.5V to VCC + 0.5V Storage Temperature Range (TSTG) ............................................ -65C to +150C Power Dissipation (PD).............................. 1500 mW Lead Temperature (TL) (Soldering, 10 sec.)..........................................260C ESD (RZAP=1.5K, CZAP=100 pF) .................... 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. DC and AC Operating Range - 5V Operation AT6002-2/4 AT6003-2/4 AT6005-2/4 AT6010-2/4 Commercial Operating Temperature (Case) VCC Power Supply Input Voltage Level (TTL) Input Voltage Level (CMOS) High (VIHT) Low (VILT) High (VIHC) Low (VILC) 0C - 70C 5V 5% 2.0V - VCC 0V - 0.8V 70% - 100% VCC 0 - 30% VCC 50 ns (max) AT6002-2/4 AT6003-2/4 AT6005-2/4 AT6010-2/4 Industrial -40C - 85C 5V 10% 2.0V - VCC 0V - 0.8V 70% - 100% VCC 0 - 30% VCC 50 ns (max) AT6002-4 AT6003-4 AT6005-4 AT6010-4 Military -55C - 125C 5V 10% 2.0V - VCC 0V - 0.8V 70% - 100% VCC 0 - 30% VCC 50 ns (max) Input Signal Transition Time (TIN) DC and AC Operating Range - 3.3V Operation AT6002-4, AT6003-4 AT6005-4, AT6010-4 Commercial Operating Temperature (Case) VCC Power Supply Input Voltage Level (TTL) Input Voltage Level (CMOS) High (VIHT) Low (VILT) High (VIHC) Low (VILC) 0C - 70C 3.3V 10% 2.0V - VCC 0V - 0.8V 70% - 100% VCC 0 - 30% VCC 50 ns (max) Input Signal Transition Time (TIN) 2-20 AT6000/LV Series AT6000/LV Series DC Characteristics - 5V Operation Symbol V IH V IL V OH V OL IOZH IOZL IIH IIL ICC CIN Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage High-Level Tristate Output Leakage Current Low-Level Tristate Output Leakage Current High-Level Input Current Low-Level Input Current Power Consumption Input Capacitance Conditions Commercial Commercial Commercial Commercial VO = VCC (max) Without Pull-Up, VO = VSS With Pull-Up, VO = V SS VIN = VCC (max) Without Pull-Up, VIN = VSS With Pull-Up, VIN = VSS Without Internal Oscillator (Standby) All Pins -10 -500 500 10 -10 -500 10 CMOS TTL CMOS TTL IOH = -4 mA, VCC min IOH = -16 mA, VCC min IOL = 4 mA, VCC min IOL = 16 mA, VCC min Min 70% VCC 2.0 0 0 3.9 3.0 0.4 0.5 10 Max VCC VCC 30% VCC 0.8 Units V V V V V V V V A A A A A A A pF 2-21 DC Characteristics - 3.3V Operation Symbol V IH V IL V OH V OL IOZH IOZL IIH IIL ICC CIN (1) Note: Parameter High-Level Input Voltage Conditions Commercial CMOS TTL Min 70% VCC 2.0 0 0 2.4 2.0 Max VCC VCC 30% VCC 0.8 Units V V V V V V Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage High-Level Tristate Output Leakage Current Low-Level Tristate Output Leakage Current High-Level Input Current Low-Level Input Current Power Consumption Input Capacitance Commercial Commercial Commercial VO = VCC (max) CMOS TTL IOH = -2 mA, VCC min IOH = -6 mA, VCC min IOL = +2 mA, VCC min IOL = +6 mA, VCC min 0.4 0.5 10 -10 -250 10 -10 -250 200 10 V V A A A A A A A pF Without Pull-Up, VO = VSS With Pull-Up, VO = V SS VIN = VCC (max) Without Pull-Up, VIN = VSS With Pull-Up, VIN = VSS Without Internal Oscillator (Standby) All Pins 1. Parameter based on characterization and simulation; it is not tested in production. 2-22 AT6000/LV Series AT6000/LV Series Device Timing: During Operation Ordering Information Usable Gates 6,000 Speed Grade (ns) 2 Ordering Code AT6002-2AC AT6002A-2AC AT6002-2JC AT6002-2QC AT6002-2AI AT6002A-2AI AT6002-2JI AT6002-2QI 6,000 4 AT6002-4AC AT6002A-4AC AT6002-4JC AT6002-4QC AT6002LV-4AC AT6002ALV-4AC AT6002LV-4JC AT6002LV-4QC AT6002-4AI AT6002A-4AI AT6002-4JI AT6002-4QI Package 100A 144A 84J 132Q 100A 144A 84J 132Q 100A 144A 84J 132Q 100A 144A 84J 132Q 100A 144A 84J 132Q Operation Range 5V Commercial (0C to 70C) 5V Industrial (-40C to 85C) 5V Commercial (0C to 70C) 3.3V Commercial (0C to 70C) 5V Industrial (-40C to 85C) 2-23 Ordering Information Usable Gates 9,000 Speed Grade (ns) 2 Ordering Code AT6003-2AC AT6003A-2AC AT6003-2JC AT6003-2QC AT6003-2AI AT6003A-2AI AT6003-2JI AT6003-2QI 9,000 4 AT6003-4AC AT6003A-4AC AT6003-4JC AT6003-4QC AT6003LV-4AC AT6003ALV-4AC AT6003LV-4JC AT6003LV-4QC AT6003-4AI AT6003A-4AI AT6003-4JI AT6003-4QI Package 100A 144A 84J 132Q 100A 144A 84J 132Q 100A 144A 84J 132Q 100A 144A 84J 132Q 100A 144A 84J 132Q Operation Range 5V Commercial (0C to 70C) Industrial (-40C to 85C) 5V Commercial (0C to 70C) 3.3V Commercial (0C to 70C) 5V Industrial (-40C to 85C) Usable Gates 15,000 Speed Grade (ns) 2 Ordering Code AT6005-2AC AT6005A-2AC AT6005-2JC AT6005-2QC AT6005A-2QC AT6005-2AI AT6005A-2AI AT6005-2JI AT6005-2QI AT6005A-2QI Package 100A 144A 84J 132Q 208Q 100A 144A 84J 132Q 208Q 100A 144A 84J 132Q 208Q 100A 144A 84J 132Q 208Q Operation Range 5V Commercial (0C to 70C) Industrial (-40C to 85C) 15,000 4 AT6005-4AC AT6005A-4AC AT6005-4JC AT6005-4QC AT6005A-4QC AT6005LV-4AC AT6005ALV-4AC AT6005LV-4JC AT6005LV-4QC AT6005ALV-4QC 5V Commercial (0C to 70C) 3.3V Commercial (0C to 70C) 2-24 AT6000/LV Series AT6000/LV Series Ordering Information Usable Gates 15,000 Speed Grade (ns) 4 Ordering Code AT6005-4AI AT6005A-4AI AT6005-4JI AT6005-4QI AT6005A-4QI AT6010-2JC AT6010A-2AC AT6010-2QC AT6010A-2QC AT6010H-2QC AT6010-2JI AT6010A-2AI AT6010-2QI AT6010-2QI AT6010-2QI 30,000 4 AT6010A-4AC AT6010-4QC AT6010-4JC AT6010A-4QC AT6010H-4QC AT6010ALV-4AC AT6010LV-4QC AT6010LV-4JC AT6010ALV-4QC AT6010HLV-4QC AT6010A-4AI AT6010-4QI AT6010-4JI AT6010A-4QI AT6010H-4QI Package 100A 144A 84J 132Q 208Q 84J 144A 132Q 208Q 240Q 84J 144A 132Q 208Q 240Q 144A 132Q 84J 208Q 240Q 144A 132Q 84J 208Q 240Q 144A 132Q 84J 208Q 240Q Operation Range 5V Industrial (-40C to 85C) 30,000 2 5V Commercial (0C to 70C) Industrial (-40C to 85C) 5V Commercial (0C to 70C) 3.3V Commercial (0C to 70C) 5V Industrial (-40C to 85C) Ordering Information Package Type 84J 100A 132Q 144A 208Q 240Q 84 Lead, Plastic J-Leaded Chip Carrier (PLCC) 100 Lead, Very Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (VQFP) 132 Lead, Bumpered Plastic Gull Wing Quad Flat Package (BQFP) 144 Lead, Thin (1.4 mm) Plastic Gull Wing Quad Flat Package (TQFP) 208 Lead, Plastic Gull-Wing Quad Flat Package (PQFP) 240 Lead, Plastic Gull-Wing Quad Flat Package (PQFP) 2-25 |
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